制造商 | 部件名 | 数据表 | 功能描述 |
Cypress Semiconductor
|
STK14C88-3 |
1Mb/18P |
256 Kbit (32K x 8) AutoStore nvSRAM Unlimited Read/Write endurance |
CY7C1541KV18 |
691Kb/27P |
72-Mbit QDR짰II+ SRAM 4-Word BurstArchitecture (2.0 Cycle Read Latency) |
CY7C1166KV18 |
874Kb/29P |
18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) |
CY7C11611KV18 |
881Kb/29P |
18-Mbit QDR짰 II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) |
CY7C1561V18 |
676Kb/28P |
72-Mbit QDR??II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) |
CY7C1546KV18 |
959Kb/31P |
72-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) |
CY7C15632KV18 |
783Kb/30P |
72-Mbit QDR짰 II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) |
CY7C1648KV18 |
857Kb/30P |
144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) |
CY7C1141V18 |
1Mb/28P |
18-Mbit QDR??II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) |
CY7C1246V18 |
1Mb/27P |
36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) |
CY7C1166V18 |
1Mb/27P |
18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) |
CY7C1261V18 |
1Mb/28P |
36-Mbit QDR??II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) |
CY7C12661KV18 |
903Kb/30P |
36-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) |
CY7C1643KV18 |
861Kb/31P |
144-Mbit QDR짰 II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency) |
CY7C1241KV18 |
913Kb/28P |
36-Mbit QDR짰 II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) |
CY7C1561V18 |
1Mb/28P |
72-Mbit QDR??II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) |
CY7C1541V18 |
1Mb/28P |
72-Mbit QDR??II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) |
CYF2018V |
943Kb/30P |
18/36/72-Mbit Programmable Multi-Queue FIFOs Independent read and write ports |
CY7C1668KV18 |
771Kb/30P |
144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) |
CY7C15632KV18 |
760Kb/30P |
72-Mbit QDR짰 II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) |