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TRANSFERS 数据表, PDF |
搜索关键字 : 'TRANSFERS' - 的资料共: 21 (1/2) Pages |
制造商 | 部件名 | 数据表 | 功能描述 |
Epson Company |
S1R72C05 |
554Kb/49P |
Support for control, bulk, interrupt, and isochronous transfers |
ATMEL Corporation |
AT91SAM9RL64 |
12Mb/903P |
Multi-layer AHB Bus Matrix for Large Bandwidth Transfers |
AT91SAM9R64 |
12Mb/903P |
Multi-layer AHB Bus Matrix for Large Bandwidth Transfers | |
Elite Semiconductor Mem... |
M13S128324A-2M |
1Mb/48P |
Double-data-rate architecture, two data transfers per clock cycle |
M13S5121632A-2S |
705Kb/48P |
Double-data-rate architecture, two data transfers per clock cycle | |
M13S2561616A-2S |
1Mb/49P |
Double-data-rate architecture, two data transfers per clock cycle | |
Winbond |
W9751G6KB-25 |
1Mb/87P |
Double Data Rate architecture: two data transfers per clock cycle |
Elite Semiconductor Mem... |
M13L32321A-2G |
1Mb/48P |
Double-data-rate architecture, two data transfers per clock cycle |
Texas Instruments |
DS92UT16 |
1Mb/111P |
UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers |
Winbond |
W9412G2IB4 |
832Kb/50P |
Double Data Rate architecture; two data transfers per clock cycle |
W9412G6JH-5 |
1Mb/53P |
Double Data Rate architecture; two data transfers per clock cycle | |
Elite Semiconductor Mem... |
M13S2561616A-2A |
1Mb/49P |
Double-data-rate architecture, two data transfers per clock cycle |
Winbond |
W972GG6JB-25 |
1Mb/87P |
Double Data Rate architecture: two data transfers per clock cycle |
W9725G6JB25I |
1Mb/86P |
Double Data Rate architecture: two data transfers per clock cycle | |
Elite Semiconductor Mem... |
M13S64164A-2Y |
1Mb/49P |
Double-data-rate architecture, two data transfers per clock cycle |
M13S128168A-2N |
720Kb/49P |
Double-data-rate architecture, two data transfers per clock cycle | |
National Semiconductor ... |
DS92UT16TUF |
1Mb/86P |
UTOPIA-LVDS Bridge for 1.6 Gbps Bi-directional Data Transfers |
Winbond |
W631GG6KB-15 |
3Mb/158P |
Double Data Rate architecture: two data transfers per clock cycle |
Elite Semiconductor Mem... |
M13L2561616A-2A |
1Mb/49P |
Double-data-rate architecture, two data transfers per clock cycle |
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